1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to field effect transistors having a reduced drain and source sheet resistance by recessing the gate electrode structure with respect to the drain and source regions.
2. Description of the Related Art
In fabricating integrated circuits having improved performance in view of operational speed and power consumption, the fabrication of field effect transistors, such as MOS transistors, is a key technology. A high operating speed in combination with an increased package density of integrated circuits requires the formation of field effect transistors having an extremely short channel length, i.e., the distance between highly doped source and drain regions forming a PN junction with an inversely doped channel region disposed therebetween. The shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith which have to be solved so as to not unduly offset the advantages obtained by minimizing the features sizes.
One problem in this respect is the requirement of extremely shallow PN junctions, that is, the depth of the source and drain regions with respect to an interface formed by a gate insulation layer and the channel region has to be decreased as the channel length is reduced. The depth of the source and drain regions, however, significantly determines the sheet resistance of these regions, and the sheet resistance may not arbitrarily be reduced by correspondingly doping the source and drain regions, since the dopants implanted into the source and drain regions at very high concentrations may not be completely activated by conventional rapid thermal anneal cycles without negatively affecting the overall dopant profile within the source and drain regions. With decreasing dimensions of the field effect transistors, the acceptable amount of diffusion of implanted dopants, also referred to as thermal budget, is also to be restricted, thereby imposing quite severe constraints on the involved anneal cycles.
Extremely shallow source and drain regions may be formed by raising the source and drain regions above the gate insulation layer/channel region interface so that the resulting sheet resistance of the enlarged source and drain regions is decreased while maintaining a required low depth of the PN junctions. Raising the source and drain regions adjacent to the gate electrode may be achieved by epitaxial growth of silicon, which, however, gives rise to a large number of problems. The epitaxial growth of the source and drain regions may produce facets or voids at interfaces with spacer elements formed adjacent to the gate electrode and silicide spikes may be formed during silicidation of the drain/source regions and the gate electrode. Additionally, during the epitaxial growth of the raised source and drain regions, dopants of extension regions formed below the spacer elements of the gate electrode may readily diffuse, thus significantly affecting the final dopant profile and also influencing the dopant concentration in the channel region. Therefore, additional adjustments of the dopant profile in the channel region are typically required. Furthermore, the epitaxial growth of the raised source and drain regions may lead to a reduced process yield due to the issues involved in precisely controlling the thickness of the epitaxial layer. In addition to the above-described disadvantages, the epitaxial growth of the raised source and drain regions significantly contributes to process complexity and tool costs.
In view of the above-identified issues in fabricating source and drain regions of reduced sheet resistance, a need exists for an improved technique that substantially avoids or at least reduces one or more of the above-identified problems.